View IS64LV25616AL-12TLA3_2620891.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. d 07/05/06 is64lv25616al issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? high-speed access time: 10, 12 ns ? cmos low power operation ? low stand-by power: less than 5 m a (typ.) cmos stand-by ? ttl compatible interface levels ? single 3.3v power supply ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? industrial temperature available ? temperature offerings: option a1: ?40 o c to +85 o c option a2: ?40 o c to +105 o c option a3: ?40 o c to +125 o c ? lead-free available 256k x 16 high speed asynchronous cmos static ram with 3.3v supply description the issi is64lv25616al is a high-speed, 4,194,304-bit static ram organized as 262,144 words by 16 bits. it is fabricated using issi 's high-performance cmos technol- ogy. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the is64lv25616al is packaged in the jedec standard 44-pin tsop type ii and 48-pin mini bga (8mm x 10mm). functional block diagram a0-a17 ce oe we 256k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb july 2006
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? truth table i/o pin mode we we we we we ce ce ce ce ce oe oe oe oe oe lb lb lb lb lb ub ub ub ub ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in pin descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a0 a1 a2 a3 a4 ce i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a5 a6 a7 a8 a9 a17 a16 a15 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a14 a13 a12 a11 a10 pin configurations 44-pin tsop (type ii)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. d 07/05/06 1 2 3 4 5 6 7 8 9 10 11 12 is64lv25616al issi ? 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 v dd v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc pin configurations 48-pin mini bga pin descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? dc electrical characteristics (over operating range) symbol parameter test conditions options min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) -0.3 0.8 v i li input leakage gnd v in v dd a1 -2 2 a a2 -5 5 a3 -10 10 i lo output leakage gnd v out v dd ,a1-22a outputs disabled a2 -5 5 a3 -10 10 notes: 1. v il (min.) = ?2.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd +0.5 v v dd v dd related to gnd ?0.3 to +4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range options ambient temperature v dd a1 ?40c to +85c 3.3v +10%, -5% a2 ?40c to +105c 3.3v +10%, -5% a3 ?40c to +125c 3.3v +10%, -5%
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. d 07/05/06 1 2 3 4 5 6 7 8 9 10 11 12 is64lv25616al issi ? capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters. power supply characteristics (1) (over operating range) -10 -12 symbol parameter test conditions options min. max. min. max. unit i cc v dd dynamic operating v dd = max., a1 ? 100 ? ? ma supply current i out = 0 ma, f = f max a2 ? ? ? 110 a3 ? ? ? 120 i sb ttl standby current v dd = max., a1 ? 50 ? ? ma (ttl inputs) v in = v ih or v il a2 ? ? ? 55 ce v ih , f = f max .a3???60 i sb 1 ttl standby current v dd = max., a1 ? 20 ? ? ma (ttl inputs) v in = v ih or v il a2 ? ? ? 30 ce v ih , f = 0 a3 ? ? ? 40 i sb 2 cmos standby v dd = max., a1 ? 15 ? ? ma current (cmos inputs) ce v dd ? 0.2v, a2 ? ? ? 25 v in v dd ? 0.2v, or a3 ? ? ? 35 v in 0.2v, f = 0 typ (2) ?5 ?5 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. shaded area product in development 2. typical values are measured at v dd = 3.3v, t a = 25 o c and not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? read cycle switching characteristics (1) (over operating range) -10 -12 symbol parameter min. max. min. max. unit t rc read cycle time 10 ? 12 ? ns t aa address access time ? 10 ? 12 ns t oha output hold time 2 ? 2 ? ns t ace ce access time ? 10 ? 12 ns t doe oe access time ? 4 ? 5 ns t hzoe (2) oe to high-z output ? 4 ? 5 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzce (2 ce to high-z output 0 4 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? ns t ba lb , ub access time ? 4 ? 5 ns t hzb (2) lb , ub to high-z output 0 3 0 4 ns t lzb (2) lb , ub to low-z output 0 ? 0 ? ns t pu power up time 0 ? 0 ? ns t pd power down time ? 10 ? 12 ns ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing and reference level 1.5v output load see figures 1 and 2 ac test loads figure 1 figure 2 319 5 pf including jig and scope 353 output 3.3v notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. 319 30 pf including jig and scope 353 output 3.3v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. d 07/05/06 1 2 3 4 5 6 7 8 9 10 11 12 is64lv25616al issi ? data valid read1.eps previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il , ub or lb = v il ) t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ub_cedr2.eps t hzb address oe ce lb , ub d out t hzce t ba t lzb t rc t pd i sb i cc 50% v dd supply current 50% t pu read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? write cycle switching characteristics (1,3) (over operating range) -10 -12 symbol parameter min. max. min. max. unit t wc write cycle time 10 ? 12 ? ns t sce ce to write end 9 ? 10 ? ns t aw address setup time to write end 8 ? 8 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pbw lb , ub valid to end of write 8 ? 8 ? ns t pwe 1 we pulse width 8 ? 8 ? ns t pwe 2 we pulse width ( oe = low) 10 ? 10 ? ns t sd data setup to write end 6 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 5 ? 6 ns t lzwe (2) we high to low-z output 2 ? 2 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. d 07/05/06 1 2 3 4 5 6 7 8 9 10 11 12 is64lv25616al issi ? write cycle no. 2 ( we controlled. oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 ( ce controlled, oe is high or low) (1 ) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? ac waveforms write cycle no. 3 ( we controlled. oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps write cycle no. 4 ( lb , ub controlled, back-to-back write) (1,3) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha notes: 1. the internal write time is defined by the overlap of ce = low, ub and/or lb = low, and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the lb , ub pins can be used to control the write function.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. d 07/05/06 1 2 3 4 5 6 7 8 9 10 11 12 is64lv25616al issi ? data retention waveform ( ce controlled) data retention switching characteristics symbol p arameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 ? 3.6 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v a1 ? 5 10 ma a2 ? ? 15 a3 ? ? 20 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 07/05/06 is64lv25616al issi ? ordering information temperature range (a1): ?40c to +85c speed (ns) order part no. package 10 is64lv25616al-10ta1 tsop (type ii) temperature range (a2): ?40c to +105c speed (ns) order part no. package 12 is64lv25616al-12ta2 tsop (type ii) is64lv25616al-12tla2 tsop (type ii), lead-free is64lv25616al-12ba2 mini bga (8mm x 10mm) temperature range (a3): ?40c to +125c speed (ns) order part no. package 12 is64lv25616al-12ta3 tsop (type ii) IS64LV25616AL-12TLA3 tsop (type ii), lead-free is64lv25616al-12ba3 mini bga (8mm x 10mm) is64lv25616al-12bla3 mini bga (8mm x 10mm), lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (48-pin) notes: 1. controlling dimensions are in millimeters. mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 7.90 8.10 0.311 0.319 d1 5.25 bsc 0.207 bsc e 5.90 6.10 0.232 0.240 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 8mm x 10mm millimeter inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 9.90 10.10 0.390 0.398 d1 5.25 bsc 0.207 bsc e 7.90 8.10 0.311 0.319 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

▲Up To Search▲

Price & Availability of IS64LV25616AL-12TLA3

	To Download IS64LV25616AL-12TLA3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .